1. Field of the Invention
The present invention relates to a motor control device for controlling the rotation of the motor.
2. Description of the Prior Art
A method for phase-controlling rotation of a motor by a PLL (phase locked loop) has been known.
FIG. 1 shows a circuit configuration thereof. X denotes a crystal oscillator for generating a reference pulse signal S.sub.X, M denotes a DC motor, and N denotes a rotating disc coaxially mounted to the motor M and having slits J rotated with the motor. The rotating disc cooperates with a photo-interrupter Q to generate a pulse signal S.sub.M at a period representing a rotating speed of the motor. Thus, the rotating disc N and the photo-interrupter Q form a photoencoder. A denotes a phase detector which detects a phase error of the motor rotation pulse signal S.sub.M from the reference pulse signal S.sub.X and supplies a phase error signal P to an adder K, and B denotes a frequency detector which converts the frequency of the motor rotation pulse signal S.sub.M supplied from the photo-interrupter Q to a voltage to supply a DC voltage V responsive to the frequency of the pulse signal S.sub.M to the adder K. A rotation error detector H which includes the phase detector A and the frequency detector B is commercially available as in integrated circuit and hence a detail thereof is not explained here. E denotes an operational amplifier, F denotes a power amplifier for driving the motor M, R1-R4 denote resistors, and C1 and C2 denote capacitors. A ratio R2/R1 represents a DC amplification factor of the operational amplifier, and a circuit Y comprising the resistor R3 and the capacitor C1 is a phase advance compensation circuit and a circuit W comprising the resistor R4 and the capacitor C2 is a phase retardation compensation circuit. Both circuits are inserted in many cases to stabilize the control system. When the control system is stable without the phase advance compensation or the phase retardation compensation, one or both of the compensation circuits may be omitted. The operation of the PLL control circuit of FIG. 1 is now briefly explained. In the PLL, when a frequency difference between the reference pulse signal S.sub.X and the motor rotation pulse signal S.sub.M is large, the phase detector A produces a beat signal corresponding to the frequency difference between both signals due to a non-linear operational characteristic of the phase detector A. If the beat frequency of the beat signal is lower than a specific frequency determined by a characteristic of a loop, the frequency difference between the motor rotation pulse signal S.sub.M and the reference pulse signal S.sub.X is reduced and the former is synchronized with the latter, but if the beat frequency is higher, a cycle slip is repeated and the frequency difference between those signals is not reduced and they are not synchronized.
FIG. 4 shows the phase error signal in the PLL phase synchronization period. S1 denotes a waveform of the beat signal and S2 denotesa DC component of the beat signal S1. If the rotation of the motor can respond to the frequency of the beat signal, the rotation speed of the motor is increased in a positive half-cycle to approach the frequency f.sub.M of the motor rotation pulse signal S.sub.M to the frequency f.sub.X of the reference pulse signal, and the rotation speed of the motor is decreased in a negative half-cycle to move the frequency of the motor rotation pulse signal S.sub.M away from the frequency of the reference pulse signal S.sub.X. In the conventional PLL which uses a sawtooth wave shape comparison, the beat signal changes slowly in the positive half-cycle and changes rapidly in the negative half-cycle, due to a response characteristic of the motor. As a result, in one cycle of the beat signal, a mean DC level offsets positively as shown by S2 in FIG. 4, and the rotation speed of the motor is increased by the DC component S2 and the frequency f.sub.M of the motor rotation pulse signal S.sub.M approaches to the frequency f.sub.X of the reference pulse signal so that the frequency difference therebetween is reduced. Thus, the beat frequency is further lowered and a larger DC component is produced. In this manner, by a positive feedback effect, the frequency of the motor rotation pulse signal accelerately follows the frequency of the reference pulse signal. This process is called a frequency pull-in period, which is represented by t1 in FIG. 4. When the frequency difference of the signals reaches a frequency which is lower than a predetermined frequency W.sub.S, the response of the rotation of the motor can perfectly follow the frequency of the beat signal and the synchronization is attained within the cycle. This process is called a phase synchronization period, which is represented by t2 in FIG. 4. The frequency difference range W.sub.S in which the frequency of the motor rotation pulse signal S.sub.M is synchronized with the frequency of the reference pulse signal S.sub.X within one or two cycles is called a lock-in range (corresponding to the phase synchronization period t2).
In the phase synchronization/pull-in period which includes the frequency pull-in period t1 and the phase synchronization period t2, as the frequency of the motor rotation pulse signal S.sub.M gradually rises, the frequency difference .DELTA.W between the reference pulse signal S.sub.X and the motor rotation pulse signal S.sub.M decreases and the synchronization is attained. A frequency difference range W.sub.P in which the phase synchronization is attained is called a pull-in range (corresponding to t1+t2). A component E1 in FIG. 4 is a steady phase error produced in the PLL in the steady rotation. When the beat frequency rises, the DC voltage generated is lowered and a longer time is required for the frequency pull-in period tl. When the frequency difference .DELTA.W of the motor rotation pulse signal S.sub.M relative to the reference pulse signal S.sub.X in the phase synchronized state, a frequency difference range W.sub.L in which the synchronization can be maintained is called a lock range. The lock range W.sub.L, the pull-in range W.sub.P and the lock-in range W.sub.S usually meet a relation of W.sub.L &gt;W.sub.P &gt;W.sub.S. Whatever wide the lock range W.sub. L is, the synchronization is hardly attained if the pull-in range W.sub.P is narrow. Accordingly, the pull-in range W.sub.P poses a design problem.
FIGS. 5(a)-5(d) show output waveforms in the circuit of FIG. 1 in the frequency pull-in period and the phase synchronization period, with the same time axis t.
FIG. 5(a) shows a waveform of the phase error signal P from the phase detector A, FIG. 5(b) shows a waveform (frequency component) of the DC voltage V representing the frequency of the pulse signal S.sub.M from the frequency detector B, FIG. 5(c) shows an output waveform of the operational amplifier E when a summation ratio of the phase error signal P to the DC voltage V is small, and FIG. 5(d) shows an output waveform of the operational amplifier when the summation ratio is large.
Components E2-E4 are steady phase errors generated in the steady rotation.
In FIG. 5(c), since the frequency component is sufficiently larger than the phase error component, the velocity control is dominant over the phase control. Thus, the pull-in range W.sub.P is wide and the phase synchronization is readily attained but an ability to compensate for the phase variation for a load variation in the steady rotation is lowered. As a result, the characteristic of the PLL cannot be fully utilized.
In FIG. 5(d), since the phase error component is large, the abllity to compensate for the phase variation for the load variation in the steady rotation is enhanced but the phase synchronization pull-in by the frequency component is no readily attained, the pull-in range W.sub.P and the lock-in range W.sub.S are narrowed, and the phase synchronization pull-in is hardly attained or cannot be attained in certain cases.
As described above, in the PLL control, the phase synchronization pull-in characteristic and the phase variation compensation characteristic in the steady rotation are usually incompatible to each other, and when one characteristic is improved, the other characteristic is deteriorated. Thus, the only solution is to find out a compromise point for both characteristics during the design.
FIG. 2 shows a prior art circuit configuration which facilitates the phase synchronization with a large summation ratio of the phase error component. The like elements to those shown in FIG. 1 are designated by the like numerals and the explanation thereof is omitted. S denotes a frequency comparator which exactly detects the frequency f.sub.MO of the motor rotation pulse signal S.sub.M from the photointerrupter Q and compares it with the frequency f.sub.O of the motor rotation pulse signal S.sub.M at a target control rotating speed and the pull-in range W.sub.P. When f.sub.MO &lt;f.sub.O -W.sub.P, that is, when the rotating speed of the motor M is too low to reach the pull-in range W.sub.P, a 3-position relay T having terminals T1, T2 and T3 select the terminal T1 to disconnect the loop to effect an open control so that the motor rotating speed is increased. When f.sub.MO &gt;f.sub.O +W.sub.P, that is, when the motor rotating speed is so high that the frequency exceeds the pull-in range W.sub.P, the relay T selects the terminal T3 to disconnect the PLL loop and effect the open control so that the motor rotating speed is decreased. When f.sub.O -W.sub.P .ltoreq.f.sub.MO .ltoreq.f.sub.O +W.sub.P, the relay T selects the terminal T2 to form the PLL loop and effect a closed control so that the PLL control is effected. As described above, since the frequency f.sub.MO of the motor rotation pulse signal S.sub.M is within the pull-in range W.sub.P, the phase synchronization pull-in is attained. In this manner, the frequency f.sub.MO of the motor rotation pulse signal S.sub.M is detected by the frequency comparator S and the control loop is opened or closed depending on the detected frequency.
However, the configuration of FIG. 2 has the following disadvantage. In many cases, the pull-in range W.sub.P is a very narrow range which is less than 0.5% of the frequency f.sub.O of the motor rotation pulse signal at the target control rotating speed. As a result, the frequency comparator S must generate a reference signal ##EQU1## and a reference signal ##EQU2## from a frequency of a crystal oscillator divided by a counter, in order to compare them with f.sub.MO. Therefore, a complex and expensive circuit is required and a compact and inexpensive motor control device is hardly attained. The pull-in range W.sub.P is experimentally determined and the experimentally determined pull-in range does not always cover all worst conditions. Accordingly, the phase synchronization pull-in may not be attained in certain cases. If the frequency is compared in a much narrower range than the pull-in range in order to avoid the above problem, the frequency comparator S will be further complex and expensive. When the control loop is opened or closed, a disturbance by the switching of the relay T occurs and a smooth switching of the control loop is not attained